1. Field of the Invention
The present invention relates to a power supply apparatus.
2. Description of the Related Art
In a testing operation for a semiconductor integrated circuit that employs CMOS (Complementary Metal Oxide Semiconductor) technology such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), memory, or the like, when the circuit operates receiving the supply of a clock, electrical current flows through a flip-flop or a latch included in such a test target circuit (which will be referred to as a “DUT”, i.e., Device Under Test). When the clock is stopped, the circuit enters a static state in which the amount of current decreases. Accordingly, the sum total of the operating current (load current) of the DUT changes with time depending on the content of the test operation, and so forth.
A power supply circuit that supplies electric power to such a DUT has a configuration employing a regulator, for example. Ideally, such a power supply circuit is capable of supplying a constant voltage (or otherwise current) regardless of the load current. However, in actuality, such a power supply circuit has an output impedance that is not negligible. Furthermore, there is a non-negligible impedance component between the power supply circuit and the DUT. Accordingly, the power supply voltage fluctuates due to fluctuation in the load.
In many cases, the power supply environment provided by such a test apparatus does not match the power supply environment of the actual equipment. That is to say, it is rare for such a test power supply environment to match the power supply environment of the actual equipment. Accordingly, in many cases, even if the same load fluctuation occurs in the DUT, such a load fluctuation leads to a difference in the power supply voltage waveform between the test apparatus and the actual equipment. Such a difference in the power supply voltage waveform between the test apparatus and the actual equipment leads to the potential for an overkill problem in that a DUT to be judged as a pass is wrongly judged as a fail, and a test escape problem in that a DUT to be judged as a fail is wrongly judged as a pass.
FIG. 1 is a block diagram showing a configuration of a power supply apparatus including a compensation circuit investigated by the present inventors. A DUT 1 is arranged such that a power supply voltage VDD is supplied to its power supply terminal P1 and its ground terminal P2 is grounded. Furthermore, a test pattern STEST is supplied to an I/O terminal P3 of the DUT 1 from an unshown driver of a test apparatus.
A power supply apparatus 8 includes a main power supply 10 and a power supply compensation circuit 12. The power supply apparatus 8 supplies a power supply voltage VDD to a power supply terminal P1 of a DUT 1. The output terminal of the main power supply 10 is coupled to the power supply terminal P1 of the DUT 1 via a power line. The main power supply 10 is configured as a linear regulator, a switching regulator, a combination of a digital control circuit and a digital/analog converter, or the like. The main power supply 10 controls an output voltage VOUT such that the power supply voltage VDD at the power supply terminal P1 matches a target voltage VREF.
A source current source 12b included in the power supply compensation circuit 12 switches on and off according to a control pattern SCNT1, so as to inject a pulse-shaped compensation current ISRC (source current) to the power supply terminal P1 of the DUT 1 via a different path without involving the main power supply 10. On the other hand, a sink current source 12c switches on and off according to a control pattern SCNT2, so as to draw a pulse-shaped compensation current ISINK (sink current) via a different path without involving the DUT 1.
With such an arrangement, the compensation control patterns SCNT1 and SCNT2 to be supplied to the power supply compensation circuit 12 are designed based on the test pattern STEST so as to cancel out deviation of the power supply voltage VDD that occurs according to the test pattern STEST to be supplied to the DUT 1. In the actual test operation in which the test pattern STEST is supplied to the DUT 1, the power supply compensation circuit 12 is controlled according to the control patterns SCNT1 and SCNT2. Such an arrangement allows the power supply voltage VDD to be maintained at a constant level.
In order to prevent such an overkill problem and such a test escape problem due to a difference in the power supply environment between the test apparatus and the actual equipment as described above, there is a demand for providing the test operation for such a DUT with a power supply environment that is equivalent to the actual DUT operation environment. In the present specification, an operation to be performed in order to meet such a demand will be referred to as “emulation”. With the power supply compensation circuit shown in FIG. 1, the control pattern SCNT may be designed so as to instruct the power supply compensation circuit to supply a compensation current that changes with time in order to provide a desired power supply voltage waveform, i.e., the same power supply voltage waveform as that generated in the actual equipment. Such an arrangement is capable of reproducing the power supply environment of the actual equipment.
However, with the power supply apparatus 8 shown in FIG. 1, there is a need to calculate the compensation current waveforms (i.e., the control patterns SCNT1 and SCNT2) every time the device operation condition (i.e., the test pattern STEST) is changed. This leads to a problem of high costs required in the test operation.
Furthermore, such a compensation operation is classified as a predictive control operation. Thus, such a compensation operation cannot sufficiently compensate for an unknown variation component due to individual variation of the DUT characteristics or the like. In some cases, such an arrangement cannot provide sufficient compensation precision. In order to compensate for the variation component due to such individual variation, there is a need to measure the characteristics for each DUT beforehand. Such an approach involves further increased costs required in the test operation.
Moreover, in principle, the operation of the power supply compensation circuit shown in FIG. 1 requires that the device operation condition (test pattern STEST) is known. This leads to reduction in the range of application, which is a problem.
Description has been made above regarding a problem to be solved by the present invention with reference to emulation provided by the power supply circuit for the test apparatus. However, it is possible that, in some cases, a power supply apparatus employed in other apparatuses that differ from such a test apparatus is required to emulate a different power supply environment.